Low speed synchronous serial interfaces, such as the System Peripheral Interface (SPI) and its numerous variants, are widely used for interfacing microprocessors with peripheral devices, including flash memories, sensors, data conversion devices, timing and synchronization devices, communication devices, audio codecs, and liquid crystal displays.
For some of these applications, it is desired to maximize the bandwidth of data transfers by increasing the clock rate. In a 4-wire SPI interface, this is relatively easy to achieve for master-to-slave transfers, which transmit clock and data in a source synchronous manner. Slave-to-master transfers however transmit clock and data in opposite directions, and thus suffer from the effects of round trip time delay, severely limiting performance.
A known technique to increase clock rate on SPI and similar interfaces involves modification to the master side of the interface, supporting an adjustable data sampling point. While this technique may be effective, it has some disadvantages: It has a high degree of design complexity. System integrators simply adding a new slave device to an existing SPI bus may be resistant to any master side modifications that may risk affecting communications with other devices. The required modifications may not be possible, e.g. when the master is integrated into an existing microprocessor design that does not support these features. Delaying the sampling point at the master requires the host processor to accept the data at a later point in time, which may require further, potentially infeasible system level changes or may impact system performance.